Yet another BBD question...

[Martin Czech]

:::Hi all,
:::
:::Now heres a thing... most BBD lines are clocked off two filp flop
:::outputs to get two completely non-overlapping pulse chains. But I have
:::just seen a circuit that actually goes a little further and deliberately
:::adds a bit of dead time into these pulses. So there is a point where
:::both lines are both low. I wonder what benefits this would have, perhaps
:::less signal degradation?? I use this approach in a class-D SMPS design a
:::while back, and it reduced EMC problems no end. Maybe worth a go.

This type of circuit is used in all of our CMOS ICs. The "dead" time
will be needed, if wafer parameters, clock speed, load, temperature and
voltage vary, clocks may overlap then.
The problem is that large loads like BBDs make the output slope flatter,
while the  feedback turns this into a sharper slope again. So the output
may not have reached 0 or VDD, but the input thinks it has.
So for large loads and flat slopes (EMC!) the feedback input inverters
have "strange" ratios, the point of trigger deliberately set up higher
or lower then normal.

Of course, this is no option for us. So we can only use some more 
inverter couples as delay. Anyway, one has always to check for non overlap
under all operating conditions.

m.c.