POT jitter on ADC???

[Fraser, Colin J]

> -----Original Message-----
> From: Batz Goodfortune [mailto:batzman at all-electric.com]
> Sent: 22 February 2000 05:15
> To: Harry Bissell; synth-diy at mailhost.bpa.nl
> Subject: Re: POT jitter on ADC???
> 
> Paul P also suggested that if the cap was sitting right on 
> the half LSB,
> there could be just as many problems as with no cap at all. 
> Although I'm
> pretty sure I have halved the input word (rotated right one 
> bit) before
> doing the comparison. Which means that the jitter has to be 1 
> whole LSB
> before that happens. In theory anyway. I'll have to go back 
> and check that
> I didn't do something stupid like Rotate it after I've 
> checked for a change.

If I read what you're doing right, your rotate will only remove half the
jitter.
For example, if the jitter is causing the reading to jump between 2 and 3
(10 and 11) then losing the bottom bit removes the jitter, but if the jitter
is between 3 and 4 (11 and 100) then the rotate doesn't help.
In my pot scanning code, I compare the current pot reading to the previous,
and update the value if the difference is more than 1 or less than -1.
Then rotate the result to remove the jitter completely.
This only uses a few more bytes of code, so maybe you could fit it in if you
knock something off elsewhere ?

Another thing to watch for is that some ADCs really don't like a bypass cap
sitting at the input.
Due to the internal switching action, currents can appear at the analogue
input.
These normally don't cause an error because they don't occur at a sensitive
time in the conversion process.
If you put a bypass cap on the input, it can cause charge pumping of these
currents that will introduce a conversion error.


Colin f