more VCO cores
Martin Czech
martin.czech at intermetall.de
Fri Feb 18 10:08:13 CET 2000
That's why I proposed a discrete mirror arrangement,
a npn expo converter could be used, and the switching could be done
with mosfets (no esd protection) which would totally
eliminate the current stealing problem.
Other problems like mirror errors, how to build a Wilson mirror,
and pcb leakage would come up, however.
Japanese or Siemens duals could give an answer..
But as usuall, I far too busy to even think about building it.
I need 2 lifes! Or an assistant, to solder all my crazy ideas...
Paul Perry, you recently reported about your
severall lifes. How did you do that?
Did you visit Liesl in her horror castle in L.A. for
some life prolonging magic drink?
;_>>>>
:::> 1.
:::> If the diff stage is hard overdriven, the overdriven npn can get
:::> into saturation (I hate this saturation confusion with field effect
:::> and bipolar junction transistors, I mean Ube~>Uce here).
:::> This would mean charge storage in the base and considerable slow
:::> down of input response. Could happen and would influence
:::> the high frequency response (flatten).
:::>
:::> Many bipolar diff stages use Darlingtons and I think this saturation/
:::> charge storage slowness get's worse then.
:::>
:::> 2.
:::> The diff stage sits on top of the Iabc current mirror, it is stearing
:::> the Iabc current (or some mirrored fraction) into the inverting and
:::noninverting
:::> output stage mirrors. In "linear" operation the base current is quite
:::small,
:::> but it will already add to Iabc at the diff stage tail. I think if the
:::transistor
:::> saturates (or comes closer to that), beta goes down, i.e. the base current
:::> s becomes considerable, therefore the error is considerable.
:::> This would mean problems @ low Iabc currents.
:::>
:::> 3.
:::> And of course
:::> both diff amp trannys are involved, I don't know if saturation will
:::imbalance
:::> the input stage, so symmetry of the triangle get's lost.
:::> This can happen in a weird way, depending of the actuall chip layout,
:::> I don't know which frequency range will be affected by that.
:::>
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