CMOS Enigma (at least to me...)
chordman at earthlink.net
Thu Aug 10 08:15:34 CEST 2000
For those of you with time and inclination, I have a CMOS
question that has me completely puzzled.
The circuit is a sawtooth to square converter which provides
a clock for a CMOS divide by 3 counter (subharmonic 5th).
Everything was fine with the circuit marked "FAILS" when
connected to a signal generator on the bench. Oscope
verified proper operation of the counter. But when I
connected the circuit to my FatMan, wierd stuff started
happening. The counter became erratic, toggleing sometimes
on every clock, sometimes skipping random clocks. At times
I could improve it, in fact it almost worked, simply by
bringing my hand closer to certain parts of the circuit. At
other times, my proximity would cause the circuit to fail
worse. After trying the usual troubleshooting, looking for
miswiring, crappy soldering and several different opamps and
configs, including hysteresis in the comparator (for 3 days!),
I finally stumbled across the bottom circuit which adds
what I would call "termination" to the clock driver's output.
This is the 2 10K resistors and .0047uF cap at the bottom,
just under the first flip flop.
My question: Why won't it work without this network? The
scope shows a good logic level clock without it. I turned the
scopes sweep rate up to look for glitchy edges, but I see none.
(BK Prec. 20 MHz, brand new).
BTW, the thing works, all thru the entire freq range of the
synth, so it's not that it won't work, although I fear it
may be marginal and could stop working at any moment. I
would just like to understand this better. I seem to remember
having a similar problem before, that one I fixed with a
one transistor buffer. That was differnt though, simply
converting a VCO square out to CMOS logic levels.
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