CMOS Enigma (at least to me...)

Martin Czech czech at Micronas.Com
Fri Aug 11 07:47:07 CEST 2000


You manipulate a clock via nor gate (the right one).
The is always possibly dangerous.
Could be a race, could be glitches.
Timing tiagram drawn before and checked after soldering?
Sensitivity to Vdd?


m.c.




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