CMOS Enigma (at least to me...)

[Scott Gravenhorst]

Thanks, I would like to see that.  Seomthing else I discovered.
I was using the square setting on the signal generator and it
worked perfectly.  When I switch to ramp, it goes chaotic, not
as bad as the VCO, but chaotic nonetheless.

I like Don Tillman's idea of a schmitt trigger.



harrybissell at prodigy.net wrote:
>I have a divide by 3 circuit to share if you like...
>it uses the "glitch" as a circuit feature, and has
>50% duty cycle output. If you want to see I'll post it.
>It was an old "Ideas for design" and has run for many (25)years
>in my modular...
>
>Sometimes different brands of CMOS ICs have funny responses.
>I have had some that do not behave without some capacitive loading
>in the gate...
>
>It might be a race condition also but I don't have time to
>study right now...
>
>H^)  harry
>
>
>>From: Scott Gravenhorst <chordman at earthlink.net>
>>Reply-To: chordman at earthlink.net
>>To: synth-diy at node12b53.a2000.nl
>>Subject: CMOS Enigma (at least to me...)
>>Date: Thu, 10 Aug 2000 08:15:34
>>
>>For those of you with time and inclination, I have a CMOS
>>question that has me completely puzzled.
>>
>>Look Here:
>>http://www.home.earthlink.net/~chordman/enigma.html
>>
>>The circuit is a sawtooth to square converter which provides
>>a clock for a CMOS divide by 3 counter (subharmonic 5th).
>>
>>Everything was fine with the circuit marked "FAILS" when
>>connected to a signal generator on the bench.  Oscope
>>verified proper operation of the counter.  But when I
>>connected the circuit to my FatMan, wierd stuff started
>>happening.  The counter became erratic, toggleing sometimes
>>on every clock, sometimes skipping random clocks.  At times
>>I could improve it, in fact it almost worked, simply by
>>bringing my hand closer to certain parts of the circuit.  At
>>other times, my proximity would cause the circuit to fail
>>worse.  After trying the usual troubleshooting, looking for
>>miswiring, crappy soldering and several different opamps and
>>configs, including hysteresis in the comparator (for 3 days!),
>>I finally stumbled across the bottom circuit which adds
>>what I would call "termination" to the clock driver's output.
>>This is the 2 10K resistors and .0047uF cap at the bottom,
>>just under the first flip flop.
>>
>>My question:  Why won't it work without this network?   The
>>scope shows a good logic level clock without it.  I turned the
>>scopes sweep rate up to look for glitchy edges, but I see none.
>>(BK Prec. 20 MHz, brand new).
>>
>>BTW, the thing works, all thru the entire freq range of the
>>synth, so it's not that it won't work, although I fear it
>>may be  marginal and could stop working at any moment.  I
>>would just like to understand this better.  I seem to remember
>>having a similar problem before, that one I fixed with a
>>one transistor buffer.  That was differnt though, simply
>>converting a VCO square out to CMOS logic levels.
>>
>>-- Scott Gravenhorst : On The Edge, but the Edge of What?
>>-- Linux Rex, Linux Vobiscum  |  RedWebMail by RedStarWare
>>-- FatMan: www.teklab.com/~chordman
>>-- NonFatMan: members.xoom.com/_XMCM/chordman/index.html
>>-- The 21st century does NOT start in the year 2000!!!
>>
>>
>>
>
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-- Scott Gravenhorst : On The Edge, but the Edge of What?
-- Linux Rex, Linux Vobiscum  |  RedWebMail by RedStarWare
-- FatMan: www.teklab.com/~chordman
-- NonFatMan: members.xoom.com/_XMCM/chordman/index.html
-- The 21st century does NOT start in the year 2000!!!