CMOS Enigma (at least to me...)

[Don Tillman]

   Date: Thu, 10 Aug 2000 10:06:40
   From: Scott Gravenhorst <chordman at earthlink.net>

   I suppose I wasn't completely specific about the failure mode.
   When it fails, the first two flops do totally unpredicatable
   things.  When they start doing their correct parttern, the
   last flop circuit works just fine.  You can already see the
   chaos at the first flop's Q.  That's the part that puzzles
   me.  Out of the comparator and into the nor gate and I see 
   what appears to my old eyes as a very square, glitch free
   clock at correct logic levels.

Okay then...

Barring a wiring error, it's very likely that your diode limiter after
the opamp is not limiting enough, or some ground noise is disturbing
things.  

I'd recommend getting rid of the diode and the first nor gate and
instead putting the opamp output through a few resistors to bring the
voltage swing down to -6 +/- 3 volts, and run that through a CMOS
schmitt trigger to generate a clean clock waveform.

You'll also want resistors on the opamp inputs to keep them safe from
dangerous currents.

And I'd still recommend getting rid of that timing glitch in the last
flop. 

  -- Don

-- 
Don Tillman
Palo Alto, California, USA
don at till.com
http://www.till.com