CMOS Enigma (at least to me...)

[Scott Gravenhorst]

I suppose I wasn't completely specific about the failure mode.
When it fails, the first two flops do totally unpredicatable
things.  When they start doing their correct parttern, the
last flop circuit works just fine.  You can already see the
chaos at the first flop's Q.  That's the part that puzzles
me.  Out of the comparator and into the nor gate and I see 
what appears to my old eyes as a very square, glitch free
clock at correct logic levels.


Don Tillman <don at till.com> wrote:
>   Date: Thu, 10 Aug 2000 08:15:34
>   From: Scott Gravenhorst <chordman at earthlink.net>
>
>   For those of you with time and inclination, I have a CMOS
>   question that has me completely puzzled.  
>
>   Look Here:
>   http://www.home.earthlink.net/~chordman/enigma.html
>
>   The circuit is a sawtooth to square converter which provides
>   a clock for a CMOS divide by 3 counter (subharmonic 5th).
>
>   My question:  Why won't it work without this network?  
>
>The problem is the last flop and the nor gate before it.
>
>You need to be especially careful when you gate a clock so that any
>gating happens when the clock is inactive.  Look what happens at the
>nor gate; on the rising edge of the clock pulse that drives the Q
>output of the second flop low (the "11" to "00" transistion)... the
>lower input to that gate goes low to high and nanoseconds later the
>upper input goes high to low, so you've got yourself a glitch that may
>or may not trigger the third flop.
>
>  -- Don
>
>-- 
>Don Tillman
>Palo Alto, California, USA
>don at till.com
>http://www.till.com
>
>

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