CMOS Enigma (at least to me...)

[Don Tillman]

   Date: Thu, 10 Aug 2000 08:15:34
   From: Scott Gravenhorst <chordman at earthlink.net>

   For those of you with time and inclination, I have a CMOS
   question that has me completely puzzled.  

   Look Here:
   http://www.home.earthlink.net/~chordman/enigma.html

   The circuit is a sawtooth to square converter which provides
   a clock for a CMOS divide by 3 counter (subharmonic 5th).

   My question:  Why won't it work without this network?  

The problem is the last flop and the nor gate before it.

You need to be especially careful when you gate a clock so that any
gating happens when the clock is inactive.  Look what happens at the
nor gate; on the rising edge of the clock pulse that drives the Q
output of the second flop low (the "11" to "00" transistion)... the
lower input to that gate goes low to high and nanoseconds later the
upper input goes high to low, so you've got yourself a glitch that may
or may not trigger the third flop.

  -- Don

-- 
Don Tillman
Palo Alto, California, USA
don at till.com
http://www.till.com