ODP: thru zero VCO questions

[Ingo Debus]

Harry Bissell wrote:
> 
> Boy this is a "brain booster"

...yes, indeed... :-)

> jhaible wrote:
> 
> > >Why not use a second set of comparators, outside the normal range, and
> > >brute force the flip-flop via Set and Reset inputs, which dominate the
> > >Data and Clock.
> >
> > This was my first thought as well (;->).
> > Problem is that, unlike a normal VCO, you cannot know which
> > input, preset or reset, is the right one in a certain case: It depends
> > on the current polarity of the modulation signal.

Oh, uh, now I see. Forget my 555 idea.

But still... what about using a RS flipflop *instead* of a toggle
flipflop? I mean, not an additional set of comparators. Use the polarity
of FM input to gate the two comparator's outputs to the correct (Set or
Reset) flipflop inputs. Since a RS flipflop is level-triggered, not
edge-triggered like a toggle flipflop, we don't have problems with
missing or spurius pulses.

> > You *could* detect this polarity with a comparator, of course.
> > And 3 exor gates might select reset or preset.

Problem is anyway, what happens when the FM input is near zero. Due to
offset error, it could happen that the "RS flipflop input selector"
logic described above thinks the FM input is positive while the
integrator is already moving downwards, or vice versa. This would mean,
the integrator goes lower and lower (or higher and higher) until it
reaches the limit. Perhaps it's better not to use the polarity of the FM
input for selecting the flipflop inputs but sort of a "direction
detector" at the integrators output instead.

However, "FM input near zero" means output frequency is very low. So we
just have a (hopefully) small range around 0 Hz where the oscillator
isn't accurate. Maybe that wouldn't matter at all, since we don't stay
in that range for longer time?

Ingo