ODP: thru zero VCO questions

[Roman Sowa]

Maybe a second set of comparators (window comparator) with
higher thresholds (by, say, 0.1V), so if the first set fails to toggle
the FF and integrator goes beyond first threshold, the second set
forces FF toggle. This only minimizes the risk of lockup. Not so good.
BTW VCO is locked up until FM input changes polarity again.

OR
now I get Harry's idea of pulse spray. A clock oscillator (100Hz?)
fed into AND gate, the other AND gate input goes to window comparator
output. When integrator output exceedes valid range (copmarators
thresholds) the AND gate issues next pulse. AND may be ORed with
comparators output for normal operation.
BUT
If, after this second pulse from AND, the integrator couldn't make it
below threshold, there comes another pulse making integrator
change the direction. If FM input will be close to this 100Hz,
and if appropriate phase relatioship occures, the integrator might
go faster above thresholds than back to where it belongs.
That's many IFs, but still...

Roman

-----Oryginalna wiadomooeæ-----
Od: Rene Schmitz [mailto:uzs159 at uni-bonn.de]
Wys³ano: 9 wrzeoenia 1999 16:54
Do: Haible Juergen; synth-diy at mailhost.bpa.nl
Temat: RE: thru zero VCO questions 



One has to use perhaps a mechanism to prevent the locking conditions.
I hope to find the time soon to try it out.

Bye
 René



error:asciiartisnotfully  \ uzs159 at uni-bonn.de
supportedwithyourcurrent   \ http://www.uni-bonn.de/~uzs159
displaydriversettings...    \ http://members.xoom.com/Rene_Schmitz