noiseless switching, CMOS supply rails

[Martin Czech]

:::I always thought modern CMOS could handle +/- 9V.  I think there's something 
:::about this in Don Lancaster's "CMOS Cookbook"; as long as you use the "B" 
:::(buffered) CMOS, you'll be fine with a +/- 9V supply.  And the "B" CMOS is 
:::pretty much all I've seen in the past 10 years, maybe longer.

Two comments (sorry, Mr. Superclever can't suppress this ;->)

1. You should look into the actual manufacturer spec sheet. 
   They might differ from source to source.
   Not absolute maximum, but recommended valuse, of course.

2. When looking at our new designs, we torture the chips with 
   higher voltages, eg. 7V for 5V designs. Chips have never failed
   so far. This is ok in the lab. But: 

   leaving the recommended area imposes overstress on the chip.
   Gates, wells, and input protection diffusions suffer.
   This means: acellerated aging, parameter shift, and you are
   comming closer to latchup triggering (eg. by supply transients).

   We actually use a combination of raised supply and heat to
   speed up aging, in order to estimate effects over a lifetime
   of -say- 10 years (time of duty). Obviousliy we can't wait
   that long in real time. Aging can be accellerated by x100
   or even x1000 this way.

   The maximum supply voltage if no question of buffered or unbuffered
   logic, but what the specific manufacturer process can stand.

m.c.