VC ADSR

[Fraser, Colin J]

> -----Original Message-----
> From: tomg [mailto:vco at mindspring.com]
> Sent: 04 May 1999 03:33
> To: tomg; macdonald at evenfall.com; synth-diy at mailhost.bpa.nl
> Cc: harrybissell at netscape.net
> Subject: Re: VC ADSR
> 
> Nope. Sorry I was right the first time, it does retrigger. 
> With the appropriate amount
> of keybounce, I was able to trigger it about 1/2 the time on 
> key release. I thought maybe 
> the 4052 locked out the 555 making it impossible for that to 
> happen. I was wrong, I was 
> right to begin with.
> 
> Chris,
> I am volunteering to help you straighten this out, if you 
> like. Or if you would rather
> work it out on your own, I understand. Nothing taste as good 
> as food from your
> own garden...

This VCADSR is almost identical to my own design from a couple of years ago.
I built a dual VCEG using a LM13700 instead of the 3080, and instead of the
555, I used a 4013 dual d-type flip-flop.
The flip-flop is set by the leading edge of the gate pulse, and reset by a
comparator that detects the attack peak.
No re-triggering there.
The inputs to the 4052 also have op-amps in front of each that mix a front
panel control with a modulation input for each parameter.

However, the use of OTAs as the voltage control element in VCADSRs was
discussed at length here a while back, and generally established to be 'a
bad thing' due to the changes in output offset voltage of the OTA with
changing bias currents as the EG switches between phases.
IIRC that was the impetus for Juergen to design his nifty 4 transistor
vc-element design.

I'm still using the OTA VCADSR though, and the offset problem isn't *that*
noticeable - I haven't had time to built JH's design yet.
I may not either, because I've been turned on to the idea of processor
generated EGs by the Waldorf Pulse...
More on that subject later, I think.


Colin f