Unused CMOS inputs

[Martin Czech]

> I have read that it is good practice to ground unused CMOS inputs to
> prevent unintended behaviors.  Is it also acceptable to set them to V+ or
> V-?  This would be really convenient when not using the buffers in the
> LM13700 for instance.
> 
more precisely: always keep unused inputs to the most negative potential of
the chip, ie. substrate potential for n-well process, or to the most
positive potential (n-well potential). This way either the nmos or the
pmos input transistor is totally off and the input stage and following
stages will not draw quiescent current.

The "ground" of your circuit may be something different.

And the unused pins have of course to be tied such that the logic
functionality still works. Eg. a "1" on an or gate will stop the gate
from working.

So: unused pins must be tied in the way described, otherwise the circuit will
fail with unwanted logic behaviour due to leakage currents etc. (high input
impedance) and the gate will draw exessive current (which may be harmfull
for higher supply voltages > 5V).

It is also highly recommended to tie unused ttl inputs as well to avoid
random logic.

m.c.