VCDO menace - Episode 2

[PrioreTP1 at nswccd.navy.mil]

come on digital is no fun. you dont even need to calibrate for temperature.
Sounds pretty cool, but is 256 bits enough in the wavetable?


-----Original Message-----
From: owner-synth-diy at mailhost.bpa.nl
[mailto:owner-synth-diy at mailhost.bpa.nl]On Behalf Of jbv
Sent: Thursday, July 08, 1999 9:52 AM
To: synth-diy at mailhost.bpa.nl
Subject: VCDO menace - Episode 2


First I'd like to thank all the list members who helped me with my
question about expo conv. maths.
Thanx for helping a math disable person...

Now back to our VCDO ramblings.

In my first description, I was still using an analog VCO in order to
keep the "warm" drift of freqs
(and also to use the thing as a pitch tracker).
But we can drop this analog section (and the counter as well) and go
100% digital. The only things
missing are a CV input and an expo conv. The latter can be digitally
emulated with a 16 bits ADC and
a 64K ROM used as a table lookup. The ADC will sample the incoming CV
and its output will be used
as an adress for the ROM.
The 1st thing that comes to mind is to store in ROM the straight
corresponding expo values for the
incoming CV. But if these values are then to be used by the previously
described algorithm for
waveform generation, it's more clever to pre-compute all wavetable
increment values.

Thus, if the freq delivered by a VCO with an expo conv is :

            F = Fb x (2 ^ CV)        with Fb the freq of the VCO when CV
= 0V

and if

            Increment (in samples) = (function length * freq) / sampling
rate

then, each value stored in ROM will be calculated according to :

            Increment = (function length * (Fb x (2 ^ CV))) / sampling
rate

A 16 bits ADC gives 65536 values, roughly a 1,5258789E-4 V step for a
10V (or 9 octaves) range.
Values should be on 24 or 32 bits (in order to reduce quantization
errors). If wavetables have 256
samples, the 8 MSBs will be used for the integer part, and the other
bits for the fractional part.
Two Flash ROMs outputing 16 bits words will be used in parallel with the
same adresses (from the
ADC output) - these chips are quite cheap these days : $10 or so at
Farnell and probably cheaper
elsewhere.

Besides, if we decide that different waveforms sound the same, then we
can stick to the basic ones
(sine, tri, square and saw), and the corresponding wavetables can be
stored in the uC ROM (the
latest beasts by Scenix run at 100 MHz but feature only 2K Rom, but
that's enough for a handfull
of WT with 256 samples).

It is tempting to also emulate the expo conv via software (and drop the
ROM) but I'm afraid that
only a DSP can handle these maths in realtime (the Scenix chips use 8
bits internal registers and
don't feature any hardwired mul nor div).


So, the only thing left to the uC is interpolation and sample output.
The whole structure is now simplified as follows :

    CV input    -->    ADC    -->    ROM    -->    uC    -->    DAC

Of course, a selector will allow the choice of a specific interpolation
(truncating, rounding or
linear interpolation), and an external ROM can be added if more
wavetables are needed.
Also samples can be output through multiple DACs if several WF are
calculated simultaneously.

We can also keep the analog VCO / analog input + counter, and use a
digital switch between the
two options.

In conclusion, we have dropped every analog section (except the CV
input). But after all it's still
a VCDO...

The only drawback is that it's not too cheap ($30 for the ADC, $10 for
each ROM, $10 for uC,
$5 to $10 for each DAC, plus a few logic ICs and a couple of Xtal /
clocks...).
But it is true that these kind of chips will keep getting cheaper in the
future, while matched
transistor pairs will get harder and harder to find...


Comments / remaks are welcomed.

jbv