JH's VCO, wavetable source

[Rene Schmitz]

At 10:02 06.07.99 -0700, John Speth wrote:

>I'm assuming the "elegant solution" means that a ramp will drive an ADC 
>which will index into a ROM table whose output will go to a DAC and you get 
>a ROM defined waveform with the same frequency as the original ramp. 
> Right?
>
>If my assumption is right then I have a question...
>
>I have yet to see *the perfect* ramp and I can't see that you can 
>practically get one.  Every one I've seen (and that isn't a lot) has little 
>imperfections at the peaks and you have to deal with that finite switch 
>time too.  How do you deal with these problems?
>
The next question is how to ensure that no stored samples are skipped.
I mean the adc could perhaps output one sample twice and then jump to two
adresses above that. (Nonlinearity of the ADC.) Ok at low freq a minor
problem (just a little THD).
Then the next thing would be higher frequencies. I has been stated that the
ADC0820 can be *clocked* at 400k but how many clock cycles does a
conversion take? At least 8 or might even take 16. Assuming the conversion
takes 8 cycles you'd have a sample rate of 50kHz. At 5kHz the cycle would
consist of only 10 samples. You don't have the same time resolution as the
output frequencies aproach the sample rate. Here the HSVCO would be better. 

Just a few random thoughts.

             ,   : (uzs159 at uni-bonn.de)
|") [" |\ | ["   : (http://www.uni-bonn.de/~uzs159)
|"\ [_ | \| [_   : (http://members.xoom.com/Rene_Schmitz)