VC envelope idea

[Joachim Verghese]

Hi again,

I also built your VC lag circuit during the weekend -- couldn't
resist, it's such a clever circuit.

For the first circuit I built I used 2N3904/3906 transistors,
and it worked immediately. Then I changed to ZTX109C/214C high
gain transistors, and I got this odd diode-drop offset on the
output all the time. I changed R2 from 22K to 39K, and it worked
okay again. I wonder what this phenomenon is due to. Reverse
leakage in the transistors due to spikes at the output of U5?

Anyhow, the circuit works very well overall, slopes are RC-shaped
down to around 5 ms, below which they get linearised. There might
be some slight distortion in the RC-shape for negative slopes if
you use medium-gain PNPs, as the base current through Q1 may get
quite high (momentarily, at the beginning of the slope), but the
error is probably negligible for most applications.

Output-to-input error is very small if you match the two 100K
resistors (R6, R9), and offset performance is mainly determined
by the op-amps used.

Conclusion: Juergen is a genius. (As if there ever was any doubt
about that).  :-)

-joachim