J105

[Ian Fritz]

Magnus Danielson wrote:

> I know for a fact that the LM311 is a real noise-makes when I turn the
> FET of in the ASM-1 VCO. I get all kinds of frequencies. I haven't
> cured it but it is time to do so, I am considering a 100 nF or so
> sitting across the LM311 body.

Comparitors are notorious for oscillating as they switch. Good layout
and bypassing are absolutely necessary. I had a lot of trouble with the
LM319 in my version of this circuit. The main problem turned out to be
too large a resistor on the + input. Anyway, you have to have the power
supplies bypassed with about .1muF right at the IC pins.

> So, in true EMC spirit there is several ways to attack the problem,
> one is to ensure that it doesn't pull that much current (keep the
> capacitance of the JFET down) or we could slow down the transient.

Isn't most of the comparitor current going through its output resistor?
I don't see how the small FET capacitance is an issue here.

> Actually, if you consider the time margins we have we could reduce the
> slope of the LM311 quite a lot before it becomes a real burden on us,
> a Miller capacitor (a capacitor in the negative feedback over the
> LM311) is one possible way to acheive this. The benefit of reducing
> the slopespeed is that the current peak will be less and thus the
> source of the spike becomes less.

This might be interesting to try, but the comparitor ICs are optimized
for fast switching, so wouldn't that just be defeating the LM311's
purpose? If you want slower switching why not just use an op amp (like
some of the simple circuits you see around)?

> Just look at the slow slope (the red signal in the picture) as we
> start turning the JFET on, why not just let the turn off slope become
> something similar to cure away many problems?

I'm afraid I wasn't able to see your figure. It came through as garbage
text. 

> So, to end this little adventure, I think there are several ways to
> cure the problem and changing the slope speed rather than keeping to a
> low capacitance is one things one can do. The falltime of the raw
> sawtooth is 737 ns so a slower turnoff time is reasonble.

I wonder if you aren't confusing a couple of different effects here. The
problem with the JFET capacitance is that it couples the switching
signal (at the gate) onto the timing cap (source and drain), so it puts
glitches on the sawtooth waveform. (See Terry's earlier post on this
effect.) The JFET capacitance has a *negligible* effect on the switching
speed. The switching speed is mainly limited -- as I see it -- by (1)
the the integrator opamp's slew rate, (2) the series resistance of the
JFET and (3) the JFET's saturated current limit. I like the idea of
trying the J105 because it improves (2) and (3).  But don't overlook (1)
either. The BB OPA132 I use makes a big improvement and an OPA602 would
probably be even better.

> As this impulse moves along the -15V line it sneaks in to place we
> would not like it and there it can cause a form of syncing of the
> other oscillator.

You might try separate power lines for the LM311 (from the point where
power enters the board directly to the IC).

Good luck, and please continue to keep us informed on your experiments.

  Ian