AW: PAIA Hex VCA circuit

[Magnus Danielson]

>>>>> "HJ" == Haible Juergen <Juergen.Haible at nbgm.siemens.de> writes:

 HJ> I haven't seen the schemos (I'd like to see them, though!),
 HJ> but here is a wild guess how it might work:
 HJ> Use the GND connection as common output (you already 
 HJ> said that), use the inverter inputs as CV inputs, and the inverter
 HJ> outputs (!) as signal inputs. That way you would have a single
 HJ> n-channel MOSFET (as VC resistor) between your signal
 HJ> inputs (i.e. inverter outputs) and the common output (i.e. 
 HJ> inverter GND). No idea *if* this works, but given the fact that
 HJ> you can use the cip as hex vca, this might be the way to do it.
 HJ> You'd best connect the "GND" output to a virtual GND (opamp)
 HJ> summing node to avoid crossmodualtion between the individual 
 HJ> signals.

This is exactly how I preceived it. I would feed the input with CV
through a 100 kohm resistor and also feed the signal into the input
through a 100 kohm resistor, this way would the N-channel MOSFET be
linearized. If you do not feed too hot signals on this, it will act in
the linear region of the FET curve, so it would actually work as well
as a single FET, but here you got 6 of them wired up for a fairly
small price. Important not is however that this only works well with
the unbuffered 4069, the buffered one is not as fun (to say the least).

It's wild, it's hilarious... got to try just for the sake of it ;)

Cheers,
Magnus