AW: [Re: thermal tips re expo converters:]

[terry michaels]

Message text written by INTERNET:ijfritz at earthlink.net
>Juergen --

Thanks for the further clarification and especially for the simulation
results!

I think some things could be done to increase the cooling rate.  One --
as I saw mentioned elsewhere -- would be to use fat heavy traces and
pads off of all the pins. Another might be to remove some of the plastic
from the package. Third, a chimney over the chip could provide a laminar
flow cooling draft while at the same time reducing fluctuations due to
air turbulence. 

What so you think?

  Ian
<

Hi Ian:

I'm not sure I fully agree with you on this.  I don't believe you need a
high cooling rate to achieve loop stability, it can be done with the proper
choice of loop compensation.  I haven't run the math for this, but I can
think of two real world examples of how this can work.

Hewlett Packard makes high stability crystal oscillators for test equipment
where the oscillator is packed in a metal container, and is VERY well
insulated.  They use long, thin wires to connect the oscillator to the pins
on the container, to cut heat loss.  As far as I know, it's stable.

An electrical analogy to this is a high current regulated power supply, say
using a 723 regulator chip driving some 2N3055 pass transistors.  It will
typically have a small cap on the output to improve transient response. 
This capacitor holds electrical charge, same as an insulated expo convertor
holds heat.  If you turn on the power supply with no load attached the
output cap comes up to the output voltage extremely fast, because such a
power supply can deliver amps of current.  The curent drain is almost
nothing, maybe milliamps or less.  That's equivilant to high thermal
insulation.  The output voltage is stable, I've never seen a power supply
break into oscillation when no load is attached.

I might be completely wrong on this, but I think a heated expo convertor
should be designed with a high current supply so it heats quickly, and high
thermal isolation so it is less affected by ambient temperature changes,
uses less current to maintain temperature, there is less error between the
set point temperature and actual chip temperature, and the entire chip is
at the same temperature, with no gradients across the chip.

BTW, a possible drawback to using fat heavy traces to create a thermal
drain is you might end up with a thermal gradient across the chip.  This
gradient will vary with the difference between ambient temp and chip temp. 
If the chip geometry is such that this gradient causes a temperature
difference between the expo transistor and the transistor that generates
the Vbe offset, you will have poor VCO stability.

Terry Michaels