EH 16 second dly

[Ingo Debus]

Haible Juergen wrote:
> Typically you have an "analogue" range (master clock modulation) of 2:1 or
> 4:1, and the rest is done with adress limitation.

I see two ways how this could be done.
First is, use the same address for read and write; read first, then
write. To control the delay time, the address counter is reset at a
certain address. Is that what you mean with address limitation? Some
ugly things happen when the delay time is changed: when the time is made
shorter, the effect isn't audible until the next reset of the counter.
For long delays this can take some time and then there'll be a jump in
the delay time, some longer part of the signal will just be skipped, no
matter if the delay time was changed smoothly or not. If the delay time
is made longer things are even worse. Something from the RAM which might
be in there from hours ago would be played back. On the other hand, the
"freeze" function is easy to implement: just disable the write cycle and
the delay loop will play infinitely with the actual delay time.

The other possibility is, use two different addresses for read and
write. The address counter always counts full cycle (full address range
of the RAM) and the delay time is set by the offset between the two
addresses. This should work much smoother. Now if the delay time is
changed, just single samples are skipped or repeated. The second RAM
address could be generated by an adder from the first one, or with
another counter.

In the tape echo analogy, the second possibilty is like moving the
playback head. The first possibility would be making the tape loop
shorter or longer on the fly (which is next to impossible of course).
Changing the clock rate is like changing the tape speed.

Ingo