[VC ADSR (was Pulse VCO Help)]

[Harry Bissell]

Chris: another quick note:

you need a buffer on the 6.8K/28K voltage divider- during attack the 6.8K is
in series with the 1K plus the analog switch resistances, this accounts for
almost 2mS right there. An NPN voltage follower would be fine, to give all the
charging current the cap wants.

also: make sure that at the maximum 4046 frequency that your pulse width is
near maximum (90%). the fatter pulse will give you more of the attack time,
with little (proportionally) difference at the lowest frequency. If this cuts
your attack time in half, you are in fat city (either enjoy fast attack, or
use bigger cap for longer decay times. 

G'nite now....  :-) Harry


Chris MacDonald <macdonald at evenfall.com> wrote:
Sorry for the delayed response but I wanted to say thanks to everyone
who helped out with the pulse VCO question.  All the responses were
useful and educational!

So here's a prototype circuit I have come up with (and breadboarded - it
does work) which uses this pulse VCO idea.  It is a voltage controlled
ADSR. I make no claims as to this circuits greatness or superiority to
anything else!  If you are looking for a really great VCADSR, build
JH's!  If you can help me improve this one though, or otherwise offer
suggestions or comments, I would be grateful.

http://www.evenfall.com/diy/vcadsr2.gif

The idea is to use a VCO to control an analog switch which in turn
controls the charging/discharging of a capacitor by periodically
connecting it to a voltage.  The inspiration for this idea came from
reading the Jupiter 4 service manual; the JP4 uses a somewhat similar
technique to generate its envelopes.  In the JP4 the pulses are
generated directly by the CPU and not a VCO I believe.

A 4046 is used for the VCO.  It controls a 4066 analog switch which
periodically connects a voltage to a capacitor, charging it over time in
discrete steps. A 4052 switches among the AD and R control voltages
(which are then sent to the VCO).  It also switches among the capacitor
charging voltages (ground, +V, and sustain).  The flip-flop and
comparators of a 555 are used to detect and delineate the attack phase
from the DSR phase.  The 555 output is used along with the gate signal
to control the switching of the 4052.  An expo converter followed by a
current to voltage converter is used to provide more CV range for long
envelope times.

Attack time range with the 0.22uf cap is 4 milliseconds to about 9
seconds.  Longer attack times are possible but the staircasing becomes
excessive due to the very low switching frequencies (sub 15 hz or so)
required.

I have learned a lot designing, building and testing this circuit but am
unhappy with it in several areas.

* Minimum attack time is nothing to write home about.  A smaller cap
would help obviously but then the max times are affected.

* The 4066 analog switch is mostly wasted with only one of four switches
being used.  Maybe it could be eliminated by using a discrete component
(FET)?

* The expo converter circuitry seems awkward to me.  There must be a
better way to do this?  But without it most of the CV range is "wasted"
in the fast area, i.e. it is difficult to make fine adjustments to long
envelope times.

* The envelope output is "staircased" instead of  being smooth due to
the capacitor being charged in discrete steps.  This staircasing may be
objectionable at long envelope times (low capacitor charging
frequencies) when the ADSR is being used to sweep a large range of
another module (VCF frequency or VCO pitch for example).  This is really
only noticeable (to me anyway) when the ADSR charging frequency is under
about 20 hz and the sweep range being controlled is very large, but
still - it is there.

Anyway, I had a lot of fun figuring this one out and I am hoping someone
will have suggestions, improvements, can point out areas of bad design,
etc.  :-)


Thanks,

Chris MacDonald


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