[VC ADSR (was Pulse VCO Help)]

[Harry Bissell]

Chris:
I'm not sure I'm with it... Does the 4046 have a 50% duty cycle? Or does it
fire a constant width pulse at a variable rate? I can't see how the 50% works.
There is a 1K-.001uF LPF at the input to the 4066. Why? It would seem that the
1K would be better off on the other side of the gate (by the .22) so that any
switching transients would be attenuated by the LPF there. Or 500 ohms on each
side???
Other sections of the 4066 could be used for a "kick in the pants" circuit to
improve the minimum attack time.
Another Idea would be to add additional timing caps as the attack time got
longer... you could run a higher frequency and get rid of noise.

OK. I'm back (my band was on TV so I had to go watch... well local Cable TV
but hey,  thats the promise of rock and roll...)

Now I see the "one shot" in your design, its the 1meg resistor, the gate
capacitance, and the Xor gate. Clever.

One of our list members has a circuit for getting a ramp waveform out of the
4046. If you set your oscillator well above the audible range (not ultrasonic,
but above the RC time constant of the series resistor and the cap) and then
drive the 4066 with a variable width pulse, you could get rid of all audible
zipper noise. Is it worth it? who knows. If you have a microprocessor, your
circuit is almost a freebie.

I'll probably be looking at this puppy for a long time. Its really unusual and
probably has a hundred worthwile variants. Nice work, Chris...

Harry Bissell




Chris MacDonald <macdonald at evenfall.com> wrote:
Sorry for the delayed response but I wanted to say thanks to everyone
who helped out with the pulse VCO question.  All the responses were
useful and educational!

So here's a prototype circuit I have come up with (and breadboarded - it
does work) which uses this pulse VCO idea.  It is a voltage controlled
ADSR. I make no claims as to this circuits greatness or superiority to
anything else!  If you are looking for a really great VCADSR, build
JH's!  If you can help me improve this one though, or otherwise offer
suggestions or comments, I would be grateful.

http://www.evenfall.com/diy/vcadsr2.gif

The idea is to use a VCO to control an analog switch which in turn
controls the charging/discharging of a capacitor by periodically
connecting it to a voltage.  The inspiration for this idea came from
reading the Jupiter 4 service manual; the JP4 uses a somewhat similar
technique to generate its envelopes.  In the JP4 the pulses are
generated directly by the CPU and not a VCO I believe.

A 4046 is used for the VCO.  It controls a 4066 analog switch which
periodically connects a voltage to a capacitor, charging it over time in
discrete steps. A 4052 switches among the AD and R control voltages
(which are then sent to the VCO).  It also switches among the capacitor
charging voltages (ground, +V, and sustain).  The flip-flop and
comparators of a 555 are used to detect and delineate the attack phase
from the DSR phase.  The 555 output is used along with the gate signal
to control the switching of the 4052.  An expo converter followed by a
current to voltage converter is used to provide more CV range for long
envelope times.

Attack time range with the 0.22uf cap is 4 milliseconds to about 9
seconds.  Longer attack times are possible but the staircasing becomes
excessive due to the very low switching frequencies (sub 15 hz or so)
required.

I have learned a lot designing, building and testing this circuit but am
unhappy with it in several areas.

* Minimum attack time is nothing to write home about.  A smaller cap
would help obviously but then the max times are affected.

* The 4066 analog switch is mostly wasted with only one of four switches
being used.  Maybe it could be eliminated by using a discrete component
(FET)?

* The expo converter circuitry seems awkward to me.  There must be a
better way to do this?  But without it most of the CV range is "wasted"
in the fast area, i.e. it is difficult to make fine adjustments to long
envelope times.

* The envelope output is "staircased" instead of  being smooth due to
the capacitor being charged in discrete steps.  This staircasing may be
objectionable at long envelope times (low capacitor charging
frequencies) when the ADSR is being used to sweep a large range of
another module (VCF frequency or VCO pitch for example).  This is really
only noticeable (to me anyway) when the ADSR charging frequency is under
about 20 hz and the sweep range being controlled is very large, but
still - it is there.

Anyway, I had a lot of fun figuring this one out and I am hoping someone
will have suggestions, improvements, can point out areas of bad design,
etc.  :-)


Thanks,

Chris MacDonald


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