AW: VC delay module ideas?

[Magnus Danielson]

>>>>> "HJ" == Haible Juergen <Juergen.Haible at nbgm.siemens.de> writes:

 >> The design I have has a very small delay between the end of one
 >> pulse and the start of the complementary pulse - this is supposed
 >> to be required for the correct operation of the BBD, ie the
 >> switches before and after each 'bucket' must not be on at the same time.
 >> 
 >> Is this not the case ?

 HJ> Good question !
 HJ> I've heard this, too, and I have seen more or less complicated designs
 HJ> that take this into account somehow. I've also seen plenty of simple 4013
 HJ> circuits, built two of them myself, so it definetly works. But I don't
 HJ> know if I loose something (decreased SNR, increased insertion loss ?)
 HJ> or not.

This comes from how the BBD chain works. There is two basic types of
chains, one where you run a three phase clock (with 0, 120 and 240 degree
phase shift) and one where you run a dual clock (with 0 and 180 degree
phase shift). The three phase clock system will run with one cell as
protection cell and the charge is moved over from one cell to another
cell. This system is pretty stable. The dual phase system has harder
restrictions on clocks, yet it seems to be more popular. What the
clock skew will result in is leakage between neighbor cells, this will
have effect on the high-end of the signal since it act as a sort of
lowpass (think in terms of a FIR filter). The leakege in one cell
transition may not be large, but now that you have that happening in
1024 cells in a row makes the leakage occur 1024 times and thus the
leakage can be quite noticable.

This is a large issue for all those CCD cameras which use basically
the same mechanisms. You can read more about it in any good university
book on semiconductors. In CCD cameras the same trouble with clocks
will manifest itself as reduced sharpness in the picture.

 HJ> Both clock lines being not allowed to be active at the same time makes
 HJ> sense. A Flipflop should do this. But why the gaps (delays) ? 
 HJ> I guess (but I don't know) it's because of the high capacitive load that
 HJ> this bunch of MOS gates form together. So both rising and falling
 HJ> edges of the clock would have increased slew rate, and there would
 HJ> be some overlap. Haven't calculated anything, but it surely will grow
 HJ> worse with longer BBD lines. Maybe that's why you often find simple
 HJ> 4013's (or just the complementary outputs of a discreet astable
 HJ> multivibrator) on short lines, and high current buffers or even special
 HJ> circuits for longer lines.
 HJ> When the Panasonic chips were introduced, there was this cheap, 
 HJ> special clock chip (forgot the part number), so that you didn't need 
 HJ> to go discreet or standard CMOS, even for short lines. Don't know if
 HJ> this has the gaps between the clocks or not. But this chip is not
 HJ> that good for wide range VCOs, I think. Roland has built a handful
 HJ> of transistors around the chip even for chorus applications. 

 HJ> If someone is going to make measurements / comparison regarding
 HJ> gaps in the dual clock scheme, I'm interested in the results !

There could possibly be a difference between these devices, however I
think that this is mostly a systematic trouble. It is still a clue
that they doesn't create the dual or tripple clocks on-chip.

Cheers,
Magnus