AW: VC delay module ideas?

[Martin Czech]

> Good question !
> I've heard this, too, and I have seen more or less complicated designs
> that take this into account somehow. I've also seen plenty of simple 4013
> circuits, built two of them myself, so it definetly works. But I don't
> know if I loose something (decreased SNR, increased insertion loss ?)
> or not.

If a two phase clock is required it is allways a good idea to have
nonoverlapping pulses. The simple flip-flop with crosscoupled feedback
does it.  A longer non-overlapping-time (flatter slopes) can be obtained
just by using inverters in the feedback paths. We do this all day in
our CMOS-VLSI chips, there's no other way to get non-overlapping on chip.

m.c.