VC delay module ideas?

[Fraser, Colin J]

> -----Original Message-----
> From: Haible Juergen [mailto:Juergen.Haible at nbgm.siemens.de]
> Sent: 30 October 1998 15:05
> To: DIY; Fraser, Colin J
> Subject: AW: VC delay module ideas?
> 

> I've heard this, too, and I have seen more or less complicated designs
> that take this into account somehow. I've also seen plenty of 
> simple 4013
> circuits, built two of them myself, so it definetly works. But I don't
> know if I loose something (decreased SNR, increased insertion loss ?)
> or not.

The circuit with the delay is pretty simple - it uses a simple RC delay
between two flip-flops (can't remember if they were 7474 or 4013).

> I guess (but I don't know) it's because of the high 
> capacitive load that
> this bunch of MOS gates form together. So both rising and falling
> edges of the clock would have increased slew rate, and there would
> be some overlap. 

IIRC there is a difference between rise and fall times that causes an
overlap - need to check the article.

> When the Panasonic chips were introduced, there was this cheap, 
> special clock chip (forgot the part number), so that you didn't need 
> to go discreet or standard CMOS, even for short lines. Don't know if
> this has the gaps between the clocks or not. But this chip is not
> that good for wide range VCOs, I think.

I've used these chips (MN3011?)- there is no provision for vc, tho' you can
inject current into the timing cap for limited vc, enough for modulation of
a chorus/flange/phaser at least.
The clock chip also provides the optimum supply voltage for the BBD relative
to the clock level ( 1 volt less IIRC).

> If someone is going to make measurements / comparison regarding
> gaps in the dual clock scheme, I'm interested in the results !

Me too.

In the meantime I'll look out the clock+delay circuit and see if I can get
it into electronic form.

Colin f