AW: VC delay module ideas?

Haible Juergen Juergen.Haible at nbgm.siemens.de
Fri Oct 30 16:05:04 CET 1998


	>The design I have has a very small delay between the end of one
pulse and
	>the start of the complementary pulse - this is supposed to be
required for
	>the correct operation of the BBD, ie the switches before and after
each
	>'bucket' must not be on at the same time.
	>
	>Is this not the case ?

Good question !
I've heard this, too, and I have seen more or less complicated designs
that take this into account somehow. I've also seen plenty of simple 4013
circuits, built two of them myself, so it definetly works. But I don't
know if I loose something (decreased SNR, increased insertion loss ?)
or not.
Both clock lines being not allowed to be active at the same time makes
sense. A Flipflop should do this. But why the gaps (delays) ? 
I guess (but I don't know) it's because of the high capacitive load that
this bunch of MOS gates form together. So both rising and falling
edges of the clock would have increased slew rate, and there would
be some overlap. Haven't calculated anything, but it surely will grow
worse with longer BBD lines. Maybe that's why you often find simple
4013's (or just the complementary outputs of a discreet astable
multivibrator) on short lines, and high current buffers or even special
circuits for longer lines.
When the Panasonic chips were introduced, there was this cheap, 
special clock chip (forgot the part number), so that you didn't need 
to go discreet or standard CMOS, even for short lines. Don't know if
this has the gaps between the clocks or not. But this chip is not
that good for wide range VCOs, I think. Roland has built a handful
of transistors around the chip even for chorus applications. 

If someone is going to make measurements / comparison regarding
gaps in the dual clock scheme, I'm interested in the results !

JH.




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