AW: 2040 filter clone with unmatched transistors ?
Haible Juergen
Juergen.Haible at nbgm.siemens.de
Thu Oct 1 18:07:31 CEST 1998
>Last time I built a 2040-type filter I used EN2016 and EP2015
arrays
>(from Elantec) with delta Vbe up to 4 mV, i.e. not perfect
matching,
>but good thermal tracking.
>
>The resulting CV feedthrough, without trimming each stage, was
around
>1.5 volts using the resistor values shown in the data sheet
application
>circuit. Quite a lot, but in other respects the filter performed
well.
Joachim, thanks for sharing your results; I have to admit that
I have never really measured CV feedthru on my filter.
>> The SSM2024 aparently solves this problem by using a much smaller
internal
>> positive supply voltage for the pnp current mirror ...
>
>Yes, and ARP's early discrete VCA (4019) had balanced, virtually
>constant potentials across the entire gain cell, if I remember
>correctly. But then again, this VCA, being part of the 2600 signal
>chain, is a DC-coupled design, so it's important to have good CV
>rejection.
This is interesting, too. Never seen this circuit - well not aware of having
it seen at least.
BTW, the 2024 method would probably not be good for the 2040, because
it would clip the other end of the signal as well.
But I have probably found another method that should work with the 2040.
(1) Use a 3-transistor (is that "Wilson" ?) pnp current mirror. This is
nothing
new, 'cause the SSM2040 has it. I thought I wouldn't need it, because I have
high beta pnps, but the 3rd transistor will also solve the Vce problem for
the pnp transistors.
(2) - and this is new - one could build a "floating cascode" for the npn's:
Don't connect the pnp current mirror output directly to the OTA output
(i.e. collector of first pnp from differential pair), but insert two diodes
in
series here. Similarly, put in an extra npn transistor into the other
collector
path of the differential pair (with emitter to collector of second pnp, and
collector
to current mirror input), and connect the base of this extra transistor to
the
anode of the upper diode. (Hope this description comes thru (;->) ). So the
npn transistor which would otherwise see approx. 14V at its collector will
now work into a cascode, at a voltage that follows the output (i.e. the
other
npn's collector). Don't ask me why exactly *two* diodes; I would have
expected one diode (to compensate the be voltage of the cascode transistor),
but with one diode the SSM2040-trademark assymmetrical clipping is not
smooth anymore; with two diodes it is.
Caveat: this is just from Spice simulation. Note that the two additional
transistors
are in a thyristor configuration, so there *might* be some unexpected side
effects.
But if the simulation tells the truth, this is a method to come very close
to the ideal
behaviour.
JH.
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