CMOS/TTL chip questions (was: Cmos Latch Octal)

[Hugo Haesaert]

Hi All !

Perhaps i was not all too clear .

While true that ultimate stability is function of the oscillator 
driving the design, i was rather referring to possible shortcomings
in the ic's themselves :

- 4017 :  looks like reset, when driven from an output, somehow 
prevents the first stage from rising at the same time as the clock, 
putting it a bit offbeat .  At least, that's what i think happens :)
The timing diagram is not very clear on this . (National 1977 cmos 
databook)

- ripple counters :  in The art of electronics there is talk of 
invalid outputs between certain counts, wrong bits going high when 
not called for .  Would this, driving a 4067 (u-boat seq design) or 
ram/rom as in the digisound or modulus 6 designs, not cause false 
triggering or non-monotonic playback of the tables ?  Or does this, 
in practicen ot cause problems ?

On "jelly-bean logic" :  at least one manufacturer sells single gate 
5 pin smd ic's .  Don't recall what family they belong to tho .

Cheers .


Keep 'em oscillating :)


Hugo
=