AW: CMOS/TTL chip questions (was: Cmos Latch Octal)

[Arthur Harrison]

-----Original Message-----
From: Martin Czech <martin.czech at intermetall.de>
To: synth-diy at mailhost.bpa.nl <synth-diy at mailhost.bpa.nl>;
theremin1 at worldnet.att.net <theremin1 at worldnet.att.net>;
Juergen.Haible at nbgm.siemens.de <Juergen.Haible at nbgm.siemens.de>
Date: Friday, November 20, 1998 4:34 AM
Subject: Re: AW: CMOS/TTL chip questions (was: Cmos Latch Octal)


>All this type A or B CMOS thing, ... ummmhh ... are you really shure that
>the *real* reason behind circuit malfunction is not a faulty PCB-Layout,
>disfunctional decoupling and other EMC malfunctions?

One such problem circuit was a very simple three IC affair to flash
four LEDs in a sequence:

*Two sections of a CD4001BE (quad 2-in NOR) used as an oscillator
 of around 4Hz,
*A CD4022BE 1-of-8 counter,
*Four sections of a ULN2004 (seven section sink driver) to drive four LEDs
 (with an appropriate current limiting resistor).

It was wirewrapped with very short 26 ga. wires, each IC decoupled with
a 0.1uF X7R ceramic cap at the socket, and supplied from a 9v alkaline
battery bypassed with 10uF solid tantalum.  Unused inputs grounded.

The miscounts were quite visibly apparent in the LED flashing pattern until
 the CD4001BE was replaced with a CD4001AE, then, no problem.

I recall trying alternative connections to the second gate inputs, i.e.,
either paralleling them to the adjacent input, or grounding them,
and also using a CD4011BE NAND instead of the CD4001BE NOR,
but this made no improvement; only the "A" parts solved the problem.
The final design used a CD4069AE; these days a CD4069UBE would
be the item.  (Those "E"s in the suffixes, BTW, just mean a plastic DIP.)

>Or simply design
>errors like races, spikes etc ? Did the design use a proper ground plane
>(yes, a double sided pcb, one side reserved for digital GND, otherwise
>hf-decoupling caps are nonsense in this frequency regions > few MHz.

Agreed re: the decoupling caps; even a few nanohenries of lead inductance
and/or the SRF of the cap defeats much of their effectiveness, but I build
them into
the WW sockets, anyway.

Note, too, that "B" gates used in non-oscillator apps (e.g., a 4011B
detecting
a coincidence at the outputs of one counter and then triggering another
counter)
never seems to cause any anomalous counts.  Such circuits were always
made with the very same construction techniques:  G10 perforated board
and 2 level WW sockets, no ground or power plane.  It seems the problem
is just when you try to use those "B" parts as 2-gate oscillators.  It may
have
something to do with the "B" parts' additional gain from their buffer
stages.

>>From my experience these are very often the reasons for digital
>misbehaviour.

>Writing this, the observations that good buffered B types with sharp
>edges cause trouble makes sense. Wrong EMC layout will only be harmfull,
>if you use fast, aggressive devices, ie. B types.

Again, however, the digital-only applications of these parts never seem to
cause problems with the given construction methods.

>By the way: I once read that Siemens nuclear power plant equipment was
>(is?)  constructet with very slow, noise suppressing and no noise causing
>logic gates.

I've resorted to very slow 74L00 parts for the same reason in some areas
where
EMC was particularly a concern.  These are no longer made, to my knowledge.

>Just my 0.01 DM.
>
>m.c.
>