AW: CMOS/TTL chip questions (was: Cmos Latch Octal)

[Martin Czech]

All this type A or B CMOS thing, ... ummmhh ... are you really shure that
the *real* reason behind circuit malfunction is not a faulty PCB-Layout,
disfunctional decoupling and other EMC malfunctions? Or simply design
errors like races, spikes etc ? Did the design use a proper ground plane
(yes, a double sided pcb, one side reserved for digital GND, otherwise
hf-decoupling caps are nonsense in this frequency regions > few MHz.

>From my experience these are very often the reasons for digital
misbehaviour.

Writing this, the observations that good buffered B types with sharp
edges cause trouble makes sense. Wrong EMC layout will only be harmfull,
if you use fast, aggressive devices, ie. B types.

By the way: I once read that Siemens nuclear power plant equipment was
(is?)  constructet with very slow, noise suppressing and no noise causing
logic gates.


Just my 0.01 DM.

m.c.