CMOS/TTL chip questions (was: Cmos Latch Octal)

[Arthur Harrison]

-----Original Message-----
From: Haible Juergen <Juergen.Haible at nbgm.siemens.de>
To: DIY <synth-diy at mailhost.bpa.nl>; Arthur Harrison
<theremin1 at worldnet.att.net>
Date: Thursday, November 19, 1998 3:56 AM
Subject: AW: CMOS/TTL chip questions (was: Cmos Latch Octal)


> >Do not clock these devices form oscillators comprised of gates
> >made of other CMOS "B" type devices, e.g., CD4001BE, CD4011BE,
> >etc.
>
>Why not ? (Didn't get the point here ...)

When I first noticed the problems caused by, for example, two
sections of a CD4011BE quad 2-in NAND used as an oscillator,
driving the clock input of a CD4017BE, I connected an oscilloscope
to the clock and tried to discern if there were any anomalies in the
transitions.  It seems that the capacitance of the probe prevented the
problem from occurring.  I believe that the scope's probe capacitance
filtered out the offending transitions, and, indeed, one fix for the
problem was to simply hang a capacitor from the clock to ground,
(Or build a scope into every circuit!)

If I recall correctly, however, the size of the capacitor had to be quite
substantial, say 0.01uF or so! That didn't make sense, since the scope's
capacitance was only about 10pF.  Possibly, the scope's loading had
some reactive term that quelled the offending glitch, but I still don't
know for sure.  One of these days, I'll have to take another look with a
better set up.

Anyway, I didn't like the idea of putting 0.01uF caps on my clock lines, so
I tried other clock schemes, and the unbuffered parts worked reliably.
The CD4069UBE hex inverter is perfect for the purpose (the CD4069AE
is an older part number for the same chip, I think).

For reference, the clock circuit is two series connected sections.  The
input of the first inverter connects to a resistor (say, 1M).  The junction
of
the two inverters connect to a second resistor (say, 100K) and the output
of the second inverter connects to a capacitor (say, 1uF, non-polar).
The other ends of the three discretes connect together, and the clock's
output is the output of the second inverter.

(I'd attempt to do an ASCII drawing, but you know what Outlook will do to
it!)

> >Race conditions occur in haphazardly-designed "asynchronous"
> >systems, where timing events aren't controlled.
>
>Yes. I had certain doubts when I replaced A-type CMOS
>with B-types in my (still unfinished) sequencer around
>the ARP Sequencer core. Fortunately it didn't cause
>problems (which speaks for ARP's design). The only
>problem was from a HC device I got from some distributor
>as a CMOS "replacement". No "74" before the "HC", then
>a 4000 number. Not this one showed strange behaviour at
>15V ! (It didn't explode, though.)
>
>JH.
>>
>