CMOS/TTL chip questions (was: Cmos Latch Octal)

[Arthur Harrison]

Regarding unequal intervals in clocked metal-gate CMOS devices
such as the CD4017BE, CD4024BE, etc:

Do not clock these devices form oscillators comprised of gates
made of other CMOS "B" type devices, e.g., CD4001BE, CD4011BE,
etc.

Also, do not clock them from (generic number) 555 timers.

Both these methods will result in erratic counts.

A better clocking method is to use an oscillator made of "A" series parts,
such as the CD4069UBE, CD4001AE, CD4011AE, etc, or, for high fixed
clock rates, a crystal oscillator module which is CMOS compatible.

Note that the part numbers I've indicated are for the original RCA
devices.  (These numbers are currently used by Harris Semiconductor,
who acquired the line, and will soon be sold to Texas Instruments)
The "A" versions of the '4000 line are hard to find sometimes, but they
have distinct characteristics that allow them to work in some applications
where the "B" parts won't.  Many replacement ICs don't even make the
distinction between the "A" and "B" parts, and some manufactures use
the "A" and "B" suffixes for denoting package types. (Lack of
standardization!)

"Timing stability" is probably not the most appropriate term when
considering these circuits.  The stability, per se, usually relates to
the system clock's frequency drift over time and temperature.
The counters themselves are extraordinarily repeatable and
reliable, provided the clock has clean edges and appropriate levels, and
the power supplies are clean and properly decoupled. Preferably, digital
systems should be constructed on a ground-plane PC board to prevent
unwanted commutation of transients caused by waveform edges.

An improperly designed digital system may be prone to erratic
behavior due to "race conditions," that is, the contention of two
nearly-simultaneous events, one or the other of which prevails
randomly, depending on noise.

Race conditions occur in haphazardly-designed "asynchronous"
systems, where timing events aren't controlled.  The use of "synchrounous"
devices, e.g., synchronous, as opposed to ripple counters, have some merit
in preventing these types of problems, although there is nothing inherently
wrong with ripple counters such as the CD4040BE, provided that the
propagation delays caused by their ripple delay are allowed for in the
design.

A tenet of well-designed synchronous logic systems is a multi-phase
timing generator which strictly govern the occurrence of all the events.

Art


-----Original Message-----
From: Hugo Haesaert <sky36919 at skynet.be>
To: Ullrich at kapsch.net <Ullrich at kapsch.net>; Adrian Corston
<adrian at internode.com.au>
Cc: synth-diy at mailhost.bpa.nl <synth-diy at mailhost.bpa.nl>
Date: Tuesday, November 17, 1998 11:51 PM
Subject: Re: CMOS/TTL chip questions (was: Cmos Latch Octal)


Hi Adrian and All !

Been looking at the schematics for sequencers .

Superseq, Serge TKB, and ETI use synchronous counters .

Practical Electronics and TomG use Johnson counter 4017 .

A design on Uboat uses ripple counter .  4040 proposed by Adrian is
also a ripple counter .

Anybody care to comment on timing stability of these ic designs in
practice .

Btw, in the 70s i constructed a metronome design from Elektor using a
4017 .  Some of my friends commented that not all steps were equal,
the reset was doin it . Did not have the means to measure this at the
time .

Thanks .


Keep 'em oscillating :)


Hugo
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