VC delay module ideas?

[Arthur Harrison]

Most certainly!  Although a flip-flop precludes the possibility
of inter-cycle glitches, and also has the advantage of free clock
and data inputs.

Art

-----Original Message-----
From: Paul Perry <pfperry at melbpc.org.au>
To: synth-diy at mailhost.bpa.nl <synth-diy at mailhost.bpa.nl>
Date: Saturday, October 31, 1998 5:13 AM
Subject: Re: VC delay module ideas?


>At 04:20 AM 1/11/98 -0800, Arthur Harrison wrote:
>
>>One quick method for making non-overlapping clocks is to run a CD4017
>>10-stage counter from a clock, and then connect the appropriate outputs
>>to a couple of FFs (CD4013, for example).  An iteration of this
>>scheme will yield a pair of rectangular waves with a 40/60 duty cycle, and
>>180 degrees out of phase with each other.
>
>Cant you just take a counter and OR the outputs in 2 batches to do this
also?
>(approximately)
>
>paul perry melb aust
>
>