TTL SRAM interfacing

[cyborg0 at GlobalEyes.net]

I have perhaps what is a somewhat unusual question.
I would like to make a analog step sequencer with memory. 
I just wonder if what I am about to try is possible, or if there is a
better way. I would also like to do it without a micro.

	In the Maplin (i think) and/or electronotes designs, they have a pulse
sent to a binary up/down counter which is then fed into 2x8 line
decoders..
I would like to know if it is feasible to just feed the output of the
binary counter into the address lines of SRAM, and, in turn, have the
SRAM data out feed into a ADC.
I decided that I only need perhaps 4-6 bits to represent 0 to 5v
accurately, therefore, I would use the remaining MSBs to select the
pattern. 

Whats cool if this works is that I could also get a bigger SRAM (say,
oh, 16 bit or something) to be able to store other types of data per
step, say, portmanto enable, extra gates, extra CVs, or have more
pattern memory.

Let me all know what you think,I need help/reassurance! I havent worked
much in design lately since my day job is all about finding new ways of
destruction rather than construction! :))

rob