Battery Backup for CMOS RAM

[Joachim Verghese]

I promised to follow up on this thread -- I've now got some circuit
examples on the web.

The first circuit <http://www.netcontrol.fi/~jocke/circuits/bbkp1.gif>
works as follows:

In normal operation, with +5V present and the -RESET signal pulled
high (inactive), Q1 conducts, thus activating the Chip Select signal
-RAMCS (active low). This also activates Q2 which pulls the RAM
supply +RAMVDD close to +5V. Since +RAMVDD is higher than the battery
voltage, diode D1 is "off".

When the -RESET signal (which should preferrably be driven by an
undervoltage detector) is taken low (active), Q1 and Q2 are
deactivated, and +RAMVDD falls to the battery voltage (approx.)
as D1 starts to conduct. As soon as Q1 stops conducting, -RAMCS
is pulled high by R1, so as to ensure that the RAM chip enters
the standby mode, and that stored data isn't affected by spurious
write pulses.

This circuit works in applications where the RAM's Chip Select
can remain activated in normal operation. If, however, the Chip
Select signal has to be controlled by the processor (or address
decoding circuitry), an OR-gate can be added as shown in
<http://www.netcontrol.fi/~jocke/circuits/bbkp2.gif>. Note
that the OR-gate package has to be powered from the backed-up
+RAMVDD line.

The capacitor and transistors should have low leakage specs -- I'm
not sure how the 2N3904/3906 shown rate in this respect, but I've
used this circuit with good results.

-joachim