Memory man or similar

[Kimmo Koli]

On Thu, 26 Feb 1998, Paul Maddox wrote:

> >
> >One interesting looking digital delay is the circuit published
> >in Electronics and Wireless World in Dec 86, a member of this
> >list on the other side of the globe (where they use to walk upside
> >down, you know) has built (and of course modified) one, here's the 
> link:
> >
> > http://www.all-electric.com/ddl.htm
> >
> >-Mikko
> 
> Looks cool, Think Im gonna build one, 256k version shouldn't be too hard 
> to impement, as I seem to have about 200 of these 41256 chips lying 
> around... anyone need any?
> If it works ok on Vero, I may even have a go at doing a PCB for it.
> 
You can also increase the delay or altenatively the S/N-ratio by modifying
the analog part. Because the delay circuit is 

   delta-sigma A/D -> 1-bit wide digital delay line -> delta-sigma D/A

you can change the one-pole low-pass filters (1Mohm and 1nF) in the input  
and the output to a second order low-pass filter (or even to higher order
one). Then you can allmost half the clock frequency for the same S/N
ratio. I suppose a cascade of two RC-networks will do the trick. The
resulting second-order delta-sigma may be unstable, so some tweaking of
the component values may be needed.
 
The other thing is that why not intentionally increase the quantization
noise of the delay with a too low clock frequency. It might be a good
effect itself. Not to mention an unstable delta-sigma A/D !

Anyway, the way the delta-sigma modulator was implemented is quite stupid
itself and many of my colleagues at our work think the same (and we've
designed and fabricated and tested several delta-sigma A/D converters).
The CMOS flip-flop works well as the comparator, so the 311 is useless.
But then of cource we need an active integrator instead or cascaded
active opamp integrators because high DC loop gain is essential for the
modulator. Anyway, the input and output integrators should be identical
for flat frequency response. 

So feel free to experiment, I'm currently too busy writing my thesis 
(but there is always time for email...)

Best regards,
-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
   Kimmo Koli                         Helsinki University of Technology 
   kimmo at ecdl.hut.fi                  Electronic Circuit Design Laboratory
   http://www.ecdl.hut.fi/~kimmo      P.O.Box 3000
   Tel:  +358 9 451 2273              FIN-02015 HUT
   Fax:  +358 9 451 2269              Finland 
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