AW: Osc reset time

[Don Tillman]

   From: Haible Juergen <Juergen.Haible at nbgm.siemens.de>
   Date: Fri, 18 Dec 1998 12:12:19 +0100

   > Don:
   >As Colin pointed out, a simultaneous triangle output would be an
   >octave below.  It would also have glitches at the peaks. 

   Why would the triangle have glitches ?

Man, what was I thinking?  I've got to remember not to post things
when I'm in a hurry.  No, no glitches at all, it's fine.

   I'd expect the *saw* wave to have a glitch, as the current source
   will make the voltage shhot up when both sides of the cap are
   momentarily disconnected. 

Right, but there's a real fast transition happening at that point on a
sawtooth wave anyway, so a glitch during at that time would, at worst,
be hard to spot.

Also, when I said that I thought that Colin's approach was how the
Exar function generator chip worked, I was wrong, but *close*!  It is
in fact very similiar to how the 4046 PLL chip works.  Most 4046 data
sheets don't show the VCO schematic, but one exception is from
National (now Fairchild):
http://www.fairchildsemi.com/ds/MM/MM74HC4046.pdf

The 4046 VCO has a positive current source, an FET switch to ground,
and a Schmitt trigger for each side of the cap.  It's a slightly
different than Colin's design -- the 4046 doesn't need the sawtooth
wave so they don't bother selecting each side of the cap and buffering
-- but it's functionally equivalent.  Alternate sides of the cap are
grounded with an FET switch, the opposite side is charged positive
with a current source, and that voltage is sampled with a comparator.

  -- Don