$5 digital delay chips

[WeAreAs1 at aol.com]

In a message dated 12/14/98 9:08:53 AM, thudson at cygnus.com wrote:

<<> Delay time is controlled by a resistor, maybe an LDR or
> OTA could be used to have a voltage controlled delay?
> 
> Add the 4164 DRAM at $1.83, and a handful of resistors
> and caps, and have a VCDD for under $20...>>

I wonder if there might be a way to connect more RAM to this chip (to double,
triple, or quadruple the maximum delay time).  Would it be possible to devise
some kind of RAS/CAS addressing circuit that would allow additional RAM chips?

For instance, if one wanted to double the max delay time, would it be possible
to simply run the RAS and CAS signals through a couple of flip-flops (set up
as divide-by-2's), and send the Q and notQ outputs of the F/F's to the
respective RAS and CAS inputs of the two RAM chips? (you would clock the F/F's
with the original RAS and CAS signals)

Or maybe - send the RAS/CAS signals through a 1-in/2-out multiplexer
(74LS157?), and switch the multiplexer *every other time* that the RAM
addresses get up to their highest count (when A0 through A? are all in high
state).  This would effectively route the RAS/CAS signal back and forth
between the two chips.  Adding additional RAM would be done by expanding the
number of multiplexer outputs.

As might be painfully obvious, I haven't really thought this out very
carefully.  Although I have done a lot of work with static RAM, I don't know
much about how dynamic RAM works.  I am especially unclear on the "refresh"
concept.  Also, I'm not sure if both RAS and CAS signals need be switched for
the above scenario to work, or if just one of them need be multiplexed.  Can
anyone offer any ideas, or a basic explanation of dynamic RAM operation?

Michael Bacich