AW: clock divider schems ...

[Haible Juergen]

	>The doubler in the VCDO is interesting. It really just makes a
spikes on
	>the rising and falling edges of the input, effectively doubling the
	>frequency, but it's a very simple circuit.
	>(You should keep in mind that these are pretty narrow output pulses
though.)
	>
	>What I've tried only as an experiment and would be neat to develop
further
	>(anyone? :) would be to cascade these doubler stages (possibly with
a one
	>shot or flip flop in between stages).
	>The input frequencies imperfections (especially from an analog vco)
could
	>be "amplified" ie:- a 2 hz deviation x2 (4hz) x2 (8hz) x2 (16hz) x2
(32hz).
	>Maybe multi-tapped outputs? Feedback loops? :)
	>
	>Any thoughts on cascaded freq doublers?

Don't know if it would work as intended.
The pulses after the first doubling are equally spaced because of the
symmetric (square wave) input signal. But for the next doubling stage,
this would not be true anymore. As you said, you'd need a monoflop 
to prolong the short pulses in order to get enough space between the
rising and falling slopes for the next edge detection / doubling stage.
After the 2nd doubling, the pulses are not equally spaced anymore.
With increasing number of doubling stages, the average distance
between two pulses will be determined more and more by the monoflop
time, and less by the period of your input signal.
This would cause some "formant" effect, similar as the ringing of a filter
with high resonance.
So I don't expect real frequency multiplying, but interesting effects
nevertheless.

JH.