pseudo-random & slow random ?

[J Brookes]

Thats true. A shift register with length N has 2**N combinations.

Actually it's (2**N) - 1, but what's that amongst friends.

The question is how to set up the feedback and exor stuff so that all
combinations are walked through.  We use such pseudo random generators
for built in self test of our dsp chips sometimes, and I have a
table somwhere  of the minimum effort of feedback circuitry for a given
lenght N. I remember that some long registers had surprisingly few feedback
expressions so it was economic to make the sequence longer !
Indeed. When N = some even number the number of taps increases quite often, 
particularly for 8, 16, 24, 32 bits. Going up a bit can often save a number 
of taps as well as increasing the cycle length. It can also be seen that 
not all bits need to be accessible, quite often only two. This would allow 
some chips to be used that don't expose all their bits to the outside 
world. The table below (from Horowitz and Hill plus some extra bits) shows 
this:

N	Length	Taps
3	7		3,2
4	15		4,3
5	31		5,3
6	63		6,5
7	127		7,6
8	255		8,6,5,4
9	511		9,5
10	1023		10,7
11	2047		11,9
12	4095		12,11,10
13	8191		13,12,11,1
14	16383		14,13,12,2
15	32767		15,14
16	65535		16,14,13,11 or 16,15,13,4
17	131071	17,14
18	262143	18,11
19	524287	19,18,17,14
20	1048575	20,17
21	2097151	21,19
22	4194303	22,21
23	8388607	23,18
24	16777215	24,23,22,17
25	33554431	25,22
26	?
27	?
28	268435455	28,25
29	536870911	29,27
30	?
31	2147483647	31,28
32	?
33	8589934591	33,20
34	?
35	34359738367	35,33
36	68719476735	36,25
37	?
38	?
39	549755813887	39,35

As Horowitz and Hill points out, a 33-bit register clocked at 1MHz would 
last over an hour. A 100-bit register clocked at 100MHz would have a cycle 
time a million times longer than the age of the universe. I don't think 
that this is going to a problem repeating somehow, not even for the longest 
sequence I could listen to.