Sample and Hold + Input Protection

[Stopp,Gene]

I've used the LF398, and it is every bit as useful as the data sheet
suggests. Just be sure to de-flux the circuit board around the holding
cap when you're done soldering, you know, the usual holding-cap-leakage
precautions.

The ASCII-gram you posted is your typical input protection scheme. I'd
probaby try a 100K in place of the 12K just to keep impedances high and
standardized - since CMOS input impedance is typically in the
billion-ohm range, this should be OK. The resistor will only kick in as
a load when the op-amp's output is between 8 and 15 volts (+ or -)
anyway.

My problem with the LM358 started when I decided to use it in single
supply mode to provide consistent logic levels of 0 or +15 to the rest
of the EG circuit. I forgot to check the databook for input voltage
ranges at different supply voltages. Turns out that when the chip is
running off of ground and V+, an input of below a diode drop below V-
(ground in this case) will cause the 358's output to go high. So
triggering with a +/-5v square wave meant that the output was either
high or high (i.e. stuck high) which of course pegs the EG at V+ with no
attack. I (dumbly) assumed that the input protection of the chip would
diode-clamp it for negative voltages. Instead it went crazy.

Therefore as you can see it is important to check the databook before
finalizing a design. In modular systems, input protection becomes an
issue more so than in a dedicated (or internally-patched) system. This
is because the patchcord can be plugged into anything, or left floating
in mid-air and subject to ambient voltages such as animal fur, kids
rubbing ballons on their tummies, or any random electron-stealing event.
Ususally for op-amps, it's sufficient to have a 100K series resistance
and that's it. CMOS, FET's, TTL, and other types of silicon may not be
as beefy and should have protection depending on the specific circuit.
Again, the databook will have all the required info for input
protection.

 - Gene