pll and phase

[Paolo Predonzani]

> 
> Any experiences with pll and PID out there ?
> 
Yes. I wrote a program one year ago to analyse the stability of a PLL.
The considered phase comparator is the state machine of the the 4046.
The loop network is a R-C-R (low pass + zero at higher freq. to improve
phase margin).
The output is a sequence of events when the state machine changes its state.
The analysis is in time domain and gives the PLL response when the input
signal has a step change in frequency.

Can it be interesting? Probably I can distribute it under GPL, but it needs
some beta-testing. 

-- 
+-------------------+----------------------------------+
| Paolo Predonzani  |  email: predo at dist.dist.unige.it |
+-------------------+         predo at acm.org            |
                    +----------------------------------+