4046 PLL and Differential Amp question

Magnus Danielson magda at it.kth.se
Tue Mar 11 23:04:37 CET 1997

>>>>> "Sas" == Synthaholic aka sPEW <chordman at concentric.net> writes:

 Sas> One of the failings of using a 4046 PLL as a frequency multiplier is
 Sas> that it's output is square.  I have an idea to get at least one more
 Sas> waveform out of it.

For it's normal purposes is square just fine...

 Sas> The capacitor connects to two pins of the IC, neither of which is
 Sas> ground.  That means the cap floats and a single ended approach would
 Sas> probably not work.

The capacitor is sees two equalent stages which consists of basically
two MOSFETs, one connected to ground and one connected to an internal
current mirror. These MOSFETs will alternate in being enabled and the
two output stages will also alternate state. The net effect is that
one end of the cap will be hooked to the ground and the other to the
current mirror, up to the point when the cap voltage get's large
enougth and the internal state-machine flipps and the cap will
effectively be reversed. The current being feed to the cap is set by
the resistors at pin 11 and 12 and by the input voltage at pin
9. Since the voltage at pin 9 is commonly a very high impedance one
you will find that it is being buffered at pin 10.

 Sas> First, I am assuming that the cap's integration voltage is not square.

True... it's a sawtooth, which can be very usefull...

 Sas> If a high input impedance differential amplifier were used, it might
 Sas> be possible to amplify the capacitor's integration voltage and supply
 Sas> a single ended output.  Do any of you have part type suggestions?  I
 Sas> am sure it will need to be a FET type at least.  Are there MOSFET
 Sas> input opamps?

What you want is some kind of JFET buffer... I would use two such
op-amps as unity buffers each end of the cap and then use a 4-resistor
and a op-amp diffrential amp stage. I would also have some reduction
of amplitude...

 Sas> Or would the S/N ratio be so bad that this would be impractical?

Well, the S/N of the cap signal itself must be low to be suitable for
a PLL cursuit, since noise there can cause jitter at the output. Most
probably will the noise induce depend on how well you do the other


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