New VC-ADSR design

[gstopp at fibermux.com]

     Hi DIY,
     
     For lack of email recently I decided that I'd try my hand at creating 
     a voltage-controlled ADSR envelope generator from scratch.
     
     The design borrows heavily from the concepts used in the ASM-1 EG, 
     such as the gate conditioner and the analog switches. The specs are as 
     follows:
     
     Control Voltage range (attack, decay, release) : 0 to 15 volts
     Minimum rise/fall time (attack, decay, release): 6.4 milliseconds
     Maximum rise/fall time (attack, decay, release): over 10 seconds
     Sustain voltage range                          : 0 to 10 volts
     ADSR Envelope output amplitude                 : 10 volts
     
     The min and max rise and fall times are determined by the integrator 
     capacitor, which can be changed in value as desired. I found the above 
     numbers to be a good compromise.
     
     The heart of the module is a voltage-controlled slew limiter identical 
     to the one found in the Electronotes Preferred Circuits Collection, 
     based on the CA3080. Analog switches are used to select whether the 
     integrator charges to V+, to the sustain voltage, or to ground. 
     Additional analog switches are used to select the voltage pot 
     appropriate to the current phase of the envelope (attack, decay, 
     release). Yet another set of analog switches is used to select 
     external control voltages for the time constants. Since the analog 
     switches are powered between +15 and ground, diodes are used on the 
     external inputs to block negative inputs. Zero volts in sets the 
     longest times; the higher the voltage, the shorter the times, with the 
     minimum times at maximum input voltage.
     
     For the attack flip/flop I used a 555 timer chip rather than the 
     CD4001 that I used in the ASM-1 EG. The 555's are a little easier to 
     get and they have a built-in reset comparator inside to boot. The only 
     drawback to the 555 is that it requires a negative-going trigger, but 
     since I like to buffer the gate with an external-signal conditioning 
     comparator anyway, I just had to swap the (+) and (-) inputs to allow 
     for the 555's preference. A buffered gate signal is provided to drive 
     a panel LED if desired.
     
     Parts count is as follows:
     
     (2) LM358 or similar single-supply dual op-amp
     (1) TL082 or similar dual-supply dual FET op-amp
     (2) CD4053 triple SPDT analog switch
     (1) 555 timer
     (1) CA3080 OTA
     (1) 2N3906 PNP transistor
     (4) 1K resistor
     (1) 2.2K resistor
     (1) 10K resistor
     (8) 100K resistor
     (2) 330K resistor
     (1) 0.001uF capacitor
     (1) 0.022uF capacitor
     (1) 0.1uF capacitor
     (4) 1N4148 diode or similar
     (1) LED for gate status
     
     This doesn't count the panel pots and jacks.
     
     I'm sure the design could be adapted to use a different OTA such as 
     the LM13600, LM13700, etc.
     
     - Gene
     gstopp at fibermux.com