CV Clock Pt.II - PW. CVPWM

[A.S.P.]

OK, I think I've decided on a design for the sequencer's clock.  It lacks 
one thing, though and that is a pulse width control, as well as a CV 
input for pulse width.  What I'd like to do is split the clock's output 
into five channels, one for clocking the sequencer, the other four to 
provide a gate output for each row.  I'd like each row to have 
independent note lengths, either controlled by a PW knob (as on the SQ10, 
ARP 1601, etc) or a CV input (as on the ARP).  

I'm looking the National Semiconducors Linear Applications databook 
(Specific IC's) and one of the Apps for the 555 looks like it will do 
just this, "When the timer is connected in the monostable mode and 
triggered with a continuous puse train, the output pulse width can be 
modulated by a signal applied to pin 5."

I'd appreciate any second opinions, as well as any leads to a simpler 
approach, if there is one.

Romeo