Good Engineering Practices

[Magnus Danielson]

> To all,
> 
> I keep hearing and reading about "Good Engineering Practices".  Short of
> taking the next five years off to get an EE degree, could we open a
> discussion about this topic where some can relate on their experiences?
> 
> Some of what I've accumulated is:
> 
> 1.  Put a large electrolytic 100 uF or larger on all supply lines to
> stabilize     the power distribution.

100uF migth very well be appropriate for some curcuits, but the value should be
increeced as the current usage of the curcuit increeses.

Also, these caps should have a smaller plastic caps put in parallel to spare
the electrolyts from fast currents. A 100nF migth be enougth for a 100uF or
even a 1000uF cap.

With plastic cap I mean a polyester, polypropylen, polystyren or something...

Why a plastic cap? Simple, they have lower loss than the ceramic ones and this
gives better highfrequency properties.

> 2.  Put .1 uF bypass (spelled ceramic disc) capacitors at various locations
> (near power connections to op amps and digital ICs) to control noise.

I'd use a plastic cap for that, but 100nF value is quite appropriate for most
applications. It migth be worth to check what is being recommended by the chip
manufacture.

The point with this cap is really to stabilize power during fast switching
events. I have myself seen how the 5V supply voltage to a memory chip diped
down to 4.5V as the outputs switched to all 1's... and boy, did the people that
designed the board got to learn how to design boards properly.... they had
never thougth of this problem as being serious before I showed them with a
oscillioscope.... that's what happends when you only know the digital design
stuff.... the system clock on that board was 20 MHz.... not all that high in
todays equipment...

The cap must be really close to the power lines of the chip due to the 
parasitic
inductors that the component legs and PCB traces have by nature. When large
current changes happen througth those wires part of the supply current will be
over those parasitic inductors. The cap will be a current reserve to keep the
voltage up....

> 3.  Have board input and output lines well separated to control crosstalk
> and     S/N ratios.

It's a good principle yes, but keeping inputs far from that 50 Hz 220 V input
is more important than keeping it from the outputs...

> 4.  Design "guard" circuits around the inputs to high quality opamps and other
>     "special" components.

The idea of useing guard traces with necessary support curcuit is certainly a
good idea, but first you must clean up the noise floor cause the errors that 
the
guard circuit would reduce could very well be below the noise/interference
signal floor... selecting components to minimize noise and makeing a wise
physical design often a very effective way to cut noise floor.

Keeping a noise and error budget througth the signal chain migth aid in finding
critical signal levels and problematic circuits. Changeing the filter 
connections migth become critical.

Cheers,
Magnus