Mad Man Rambles about Noise Generators

[Scott Gravenhorst, Synthaholic]

>   You wrote: 
>Certainly, but a shift register with just a lone inverter feedback is
>a VERY DIFFERENT THING than one with XOR feedback.
>
>Okay, imagine a 3-bit SR, shifting left to right, with an XNOR gate on
>the last two bits:

I understand the math behind the number of possible states and the 
doubling of them by adding another stage.  However, I was playing with 
a system who's output is only one bit.  I was looking at the problem 
from the standpoint of one half cycle at a time and given that each 
half cycle lasts a certain amount of time, it could be said to have a 
sort of instantaneous frequency characteristic that changes from half 
cycle to half cycle, giving rise to 'random frequency'.  I looked at 
the length of the shift register as determining the longest possible 
half cycle.

This method works well, except that when the clock frequency (and this 
is a VCO driven design) is low (can't give a value) there tends to be a 
kind of tonal thumping that goes away with lowpass filtration.  What I 
noticed is that this thumping also diminishes when I double the size of 
the register, but doesn't sound much different by adding one flop.  
There doesn't seem to be any problem if the range of clock rates 
produced by the VCO is rather high, like 2khz to 32khz.

As the circuit stands now, I get very obvious noise output changes when 
different keys are pressed.  Higher pitched noise from higher keys.  
But it's not the same as fixing the clock rate and driving a lowpass 
filter from the pitch CV.

>If the goal is to get a more analog-like signal out of this beast,

That is one, also to possibly get more than one kind of noise 
characteristic out of one system.  Or is this more easily done by 
feeding a raw noise signal into different filters?

>simply resistor-sum several arbitrarily selected bits of the shift
>register, or send those bits to a DAC.  Use XOR combinations of bits,
>AND combinations of bits, etc.

I tried the DAC method which produces a better or at least different 
characteristic sound when the clock is of a low rate.  I seems like the 
summing resistor method should also sound different from the DAC 
method.  The DAC would produce an instantaneous voltage whose value is 
determined by a binary weighted resistor ladder, but if the summing 
resistors were all the same value, the voltage would be determined by 
the sum of all the 'on' bits.  One could actually sum *all* of the 
bits.  So it would seem I can get possibly 4 outputs:  
1: just a bit, caveat: driven at a high rate.
2: DAC output.
3: Summing resistor output.
4: a PLL's demod output, (input driven by one bit).

>
>If the PLL was running in its linear range, yes, but I can't imagine
>that happing when the input is a random pulse train.  You'll be
>listening to the characteristics of a PLL attempting to lock onto
>noise.  (Which *might* sound pretty cool!)

So I am hoping!
-- 
-- Scott G., Synthaholic

If at first you don't succeed, keep suckin' 'til you do suck seed.
                                                 -- Curly Howard
What else can happen?
       -- Howard (Never call me Howie) Bradley


-- 
-- Scott G., Synthaholic

If at first you don't succeed, keep suckin' 'til you do suck seed.
                                                 -- Curly Howard
What else can happen?
       -- Howard (Never call me Howie) Bradley