Mad Man Rambles about Noise Generators

[Don Tillman]

   Date: Sun, 2 Jun 1996 08:20:58 -0700
   From: chordman at ix.netcom.com (Scott Gravenhorst, Synthaholic)

   You wrote: 

   >Ummm, no.  A shift register of 9 bits will be able to produce noise up
   >to an octave lower than an 8-bit register.

   Why?  It is not a cascaded flip flop binary counter, but rather each 
   stage passes it's bit value to the next stage on each clock.

   Let's remove the scrambling XOR feedback for a moment and consider a 
   simple 8 stage shift register.  Assume a constant clock rate and that 
   the register starts clear.  Now assert and hold a high level at the 
   input.  8 clock times later, the output of the last stage goes high.  
   Now extend it to 9 bits and do the same experiment.  Wouldn't the high 
   level appear 9 clock times later?  If a feedback loop is added without 
   XOR, but simple inversion, would this not represent a divide by 16 (8 
   clocks high, then 8 clocks low...) in the first example and a divide by 
   18 in the second?  I should think that 16 stages would be required to 
   extend the delay to double that of an 8 stage register.

Certainly, but a shift register with just a lone inverter feedback is
a VERY DIFFERENT THING than one with XOR feedback.

Okay, imagine a 3-bit SR, shifting left to right, with an XNOR gate on
the last two bits:

 000
 100
 110
 011
 101
 010
 001
 000 and cycle.

There's also a second pattern:
 111 and cycle.

So a 3-bit SR gives you a 7-cycle pattern plus a (not useful) 1-cycle
pattern.  That's 2^3 states.

Now, a 4-bit SR, same deal.

 0000
 1000
 1100
 1110
 0111
 1011
 1101
 0110
 0011
 1001
 0100
 1010
 0101
 0010
 0001
 0000 and cycle

And the secon dpattern:
 1111 and cycle.

So that's a 15-cycle pattern and a 1-cycle pattern.  That's 2^4 states.

   >>   I am also going to experiment with a PLL attached to the noise 
   >>   generator output. 
   >
   >What's the purpose of the PLL?

   Since the ouput of any stage toggles between high and low, it's output, 
   if taken to be analog, is of constant amplitude, but varying frequency. 

Ummm, no.  It's a random pulse train, there really is no frequency.
Which, when you get down to it, is the very point, right?

If the goal is to get a more analog-like signal out of this beast,
simply resistor-sum several arbitrarily selected bits of the shift
register, or send those bits to a DAC.  Use XOR combinations of bits,
AND combinations of bits, etc.

   Inputting this single bit output into one side of the PLL phase 
   comparator, the PLL demodulated output would produce a varying 
   amplitude signal of random frequency as well as random amplitude.  I 
   would think that it would have a different sound than the raw digital 
   signal of one shift register flip flop output.

   Would this be the same as simply lowpass filtration?  I don't know.  
   That's why I want to try it.

If the PLL was running in its linear range, yes, but I can't imagine
that happing when the input is a random pulse train.  You'll be
listening to the characteristics of a PLL attempting to lock onto
noise.  (Which *might* sound pretty cool!)

  -- Don