Analog Shift Register design
gstopp at fibermux.com
gstopp at fibermux.com
Tue Jan 23 23:23:21 CET 1996
Hi DIYer's,
Well another protoboard mass of wires has grown on my bench in the
lab, this time it's a four-stage analog shift register. Really it's
just four sample-and-holds in a row that are clocked in a
bucket-brigade fashion, with a variable shift rate and an external
shift input option.
(This is another circuit inspired by taking pieces of other circuits,
some from Electronotes, some from databooks, some from my brain, and
piecing them together in different ways. My main goal is a reduced
parts count for easier building. This time list member Steve Varner
asked about some chips, one of them being the LF398 Sample and Hold,
and I told him that I had bad luck with these in the past. Well,
knowing how I've screwed up in the past, I tried it again in a new
circuit, and it works great.)
The circuit consists of four LF398 Sample and Hold chips, arranged in
a row output-to-input. The sample triggers are provided by a TTL shift
register, clocked by a fixed 2 Khz oscillator. A 555 timer is used to
provide the sample command, and it has a switch that determines
whether it oscillates by itself at an adjustable rate, or conditions
an external trigger waveform.
The fixed 2 Khz oscillator is built around 1/2 of an LM358 low power
op-amp, powered between +5 and ground. The traditional linear databook
single op-amp "square wave generator" configuration is used, with
component values chosen for 2 Khz. The output of this oscillator
clocks the shift register.
The shift register used is a 74HCT164 8-stage serial-in parallel-out
shift register. Both input pins are tied together and the enable is
tied high. A set/reset flip-flop, made from a 74HCT00 quad NAND gate,
has its Q output connected to the shift register serial input. The
first parallel output of the shift register (pin 3) is tied back
around to the "reset" input of the flip-flop, thru an inverter (one of
the remaining NAND gates). When the flip-flop is set, a "1" is
presented to the shift register serial input, which gets clocked on
down the eight parallel outputs. The first output it hits resets the
flip-flop, so only a single "1" is sent down the line. Parallel
outputs 2, 4, 6, and 8 go to the sample control inputs on sample and
hold units 4, 3, 2, and 1 respectively. In this way the output of any
of the sample and hold units is passed to the one after it before it
gets a new sample command itself. This is how the bucket brigade is
implemented.
A 555 timer is set up as an astable multivibrator, and is capacitively
coupled into the "set" input of the flip-flop. The oscillation rate of
this circuit is variable between 0.1 Hz and 140 Hz. Therefore with
every cycle of the multivibrator, a "1" is passed down the shift
register and the sample and holds update. The other half of the LM358
is used as an input conditioning comparator, with a switch on the 555
that allows the internal rate circuitry to be bypassed and external
triggers to fire off the shift register.
The LF398 is an 8-pin DIP package with an analog input, an analog
output, a sample control input, and a holding capacitor pin. The chip
is powered off of +/- 15 volts, and thus the analog input range can be
within the full 30-volt power supply range. Since the shift register
is being clocked at 2 Khz, the sample pulses are 500 microseconds
wide, and a 0.01uF holding cap was found to be a good trade-off
between charge time and droop.
A possible drawback of the design is the need to have a +5 supply for
the TTL as well as +/- 12 or 15 volts. I have power supplies out the
wazoo so it's not a problem for me, but some builders may not be so
lucky. +/- 5 volt operation would probably work as well.
If you want a copy of the schematic, email with your fax #.
- Gene
gstopp at fibermux.com
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